This invention relates generally to the fabrication of semiconductor integrated circuits. More particularly, it relates to a method of filling deep and shallow trenches with an amorphous silicon through chemical vapor deposition and converting the amorphous silicon to large grain, nearly single crystalline silicon for fabrication of low resistivity contacts.
With ever increasing demand for smaller and smaller integrated semiconductor circuits, many of the features of the circuits have been fabricated with narrow trenches with vertical sidewalls to overcome the disadvantages of isolation by recessed oxidation or diffusion isolation. It has become well known in the art to provide trenches in the silicon substrate to overcome the disadvantages of the thermal oxidation. This technique typically uses a reactive ion etching (RIE) process capable of etching a silicon substrate vertically to form deep grooves of a given width having nearly vertical sidewalls. These trenches can then be filled with a variety of dielectric materials including glasses, oxides or silicon nitride. These materials however, have a tendency to leave voids inside the trench, particularly when the aspect ratio of the trench increases, i.e. the trench is relatively deep.
It is also known to use undoped chemical vapor deposited (CVD) polysilicon to fill isolation trenches. Unlike deposited glasses and oxides, CVD polysilicon tends to fill trenches with aspect ratios in the range of 4:1-5:1 easily without leaving voids inside the trench. The undoped polysilicon also has an advantage of having thermal match of the expansion coefficient with a silicon substrate.
Other features such as sublayer contacts including substrate, well and subcollector contacts can be formed in narrow trenches. One known process which provides a substrate contact using a CVD polysilicon or epitaxial silicon trench fill process is disclosed in commonly assigned U.S. Pat. No. 4,924,284, to Beyer et al. In this process, the trenches in which the substrate contacts are formed are selectively doped, either by boron diffusion from a borosilicate sidewall into the polysilicon trench fill or by an in-situ boron doped epitaxial layer. Those trenches which are used as isolation regions are not doped. It requires a high temperature (&gt;900.degree. C.) to grow epitaxial silicon. Also, surface faceting and sidewalls defect formation present problems for the above process.
While the polysilicon processes described in the U.S. Pat. No. 4,924,284 possess certain advantages for trench fill formation of sublayer contacts, they also share some drawbacks.
Most of these drawbacks relate to the granular character of the CVD polysilicon material as it is deposited. On one hand, the grain size of a polysilicon film as deposited via a CVD process is relatively small, on the order of 100 Angstroms. While a thermal anneal process can increase the grain size somewhat, it is difficult to attain the low resistivity desired in a sublayer contact because of the presence of the grain boundaries. Additional dopant becomes inactive at the grain boundaries, and thus the overall sheet resistance is gated by the grain size. On the other hand, while a larger grain size of the polysilicon is desirable for improved conductivity, the grain size limits the ability of the CVD process to provide a good trench fill. Larger grain sizes will only make this effect worse. At a 100 Angstrom grain size, the granular character of the CVD polysilicon negatively impacts the filling of trenches with aspect ratios higher than 4:1 to 5:1.
Another disadvantage with a CVD polysilicon process is that the process temperatures in the deposition process are relatively high. A typical CVD polysilicon process in the art requires temperatures in the range of 628.degree. C. for deposition. The high temperature anneal which follows is in the range of 850.degree. C. In general, lower temperature processes are desired to decrease the effects of thermal cycling on the substrate and control dopant diffusion.